1. Field of the Invention
The present invention relates to a dynamic random access memory (hereinafter referred to as "DRAM"), and particularly to a DRAM having an output control circuit for preventing undesired data from being outputted from the DRAM when an address is transited before a column address strobe signal is latched during DRAM read operation, and allowing desired data to be outputted from the DRAM when a global input/output data signal is precharged after the column address strobe signal is latched.
2. Description of the Conventional Art
Referring to FIG. 1, a conventional DRAM includes a row address buffer 10 for outputting a row address signal RADS in accordance with a row address strobe signal /RAS and an address signal ADS; a column address buffer 20 for outputting a column address signal CADS and an address transition detecting signal ATD in accordance with the address signal ADS, the row address strobe signal/RAS and a column address strobe signal/CAS; a row decoder 30 for outputting word line selection signals WLo to WLn by decoding the row address signal RADS outputted from the row address buffer 10; a column decoder 40 for outputting column selection signals YSELo to YSELm in accordance with the column address signal CADS and address transition detecting signal ATD outputted from the column address buffer 20; a memory cell 50 for outputting the stored data in accordance with the word line selection signals WL0 to WLn; first and second sense amplifiers 51 and 52 for amplifying the data outputted from the memory cell array 50, and outputting the amplified data in accordance with the column selection signals YSEL0 to YSELm outputted from the column decoder 40; a data bus sense amplifier 60 for amplifying the data outputted from the first and second sense amplifiers 51 and 52, and outputting the signals of the amplified data, i.e., first and second global input/output data signals GIO and GIO*; and an output buffer 70 for latching the first and second global input/output data signals GIO and GIO* outputted from the data bus sense amplifier 60, and outputting the latched signals from the DRAM in accordance with an output enable signal /OE.
Here, the DRAM is referred to only in case where the data stored in the memory cell array 50 is outputted. The memory cell array 50 includes a plurality of cells each storing the digital data.
The operations of the conventional DRAM are explained, referring to the drawings.
When an address signal ADS is commonly inputted to the row address buffer 10 and the column address buffer 30 as shown in FIG. 2C, and the row address strobe signal /RAS is transited from high level to low level, and becomes in active state, as shown in FIG. 2A, the row address signal RADS is latched by the row address buffer 10 and outputted to the row decoder 30. Next, the row address signal RADS is decoded by the row decoder 30, and word line selection signals WL0 to WLn corresponding to the decoded row address signals are outputted to the memory cell array 50, thereby the data of the memory cells are amplified in the first and second sense amplifiers 51 and 52.
Here, when a predetermined time tRAD elapses after the row address strobe signal /RAS is transited from high level to low level, the address signal ADS is regarded as the column address signal CADS by the column address buffer 20.
Accordingly, when the address signal ADS is transited after the lapse of a predetermined time, where the address strobe signal CAS is not in active state, the column address signal CADS and the address transition detecting signal ATD transited from high level to low level, as shown in FIG. 2D, are outputted to the column decoder 40, respectively.
Afterwards, the column address signal CADS is decoded by the column decoder 40, and the column selection signal YSELi (where, i=0, 1, . . . , m) corresponding to the decoded column address signal is outputted to the first sense amplifier 51 or the second sense amplifier 52, as shown in FIG. 2E, thereby data amplified by the first sense amplifier 51 or the second amplifier 52 is outputted to the data bus sense amplifier 60.
The data bus sense amplifier 60 amplifies the inputted data, and outputs to the output buffer 70 the first and second global input/output data signals GIO and GIO* of low level, as shown in FIG. 2F. Here, in a state precharged to high level, when the data outputted from the data bus sense amplifier 60 is "1", the first global input/output data signal GIO is transited to low level, whereas, the data outputted from the data bus sense amplifier 60 is "0", the second global input/output data signal GIO* is transited to low level.
At this time, when the output enable signal /OE is transited to low level, as shown in FIG. 2G, a signal Dout1 of undesired data latched in the output buffer 70 is outputted from the DRAM, as shown in FIG. 2H.
On the other hand, when the address signal ADS is transited again, as shown in FIG. 2C, and the column address strobe signal /CAS is transited to low level and in active state, as shown in FIG. 2B, the column address signal CADS latched by the column address buffer 20 and the address transition detecting signal ATD, i.e., pulse signal of high level are outputted to the column decoder 30, respectively.
When the address transition detecting signal ATD is transited to low level, the column selection signal YSELi (where, i=0, 1, . . . , m) corresponding to the decoded value of the column address signal CADS is outputted to the first sense amplifier 51 or the second sense amplifier 52, as shown in FIG. 2E, and the data amplified by the first sense amplifier 51 or the second sense amplifier 52 is outputted to the data bus sense amplifier 60.
Next, the data bus sense amplifier 60 amplifies the inputted data, and outputs to the output buffer 70 the first and second global input/output data signals GIO and GIO* of low level, as shown in FIG. 2F.
At this time, as shown in FIG. 2G, since the output enable signal /OE is maintained in low level, a signal Dout2 of desired data latched in the output buffer 70 is outputted from the DRAM, as shown in FIG. 2H.
Here, when the row address strobe signal /RAS and the column address strobe signal /CAS are transited to high level, the address transition detecting signal ATD is transited to high level.
However, the conventional DRAM has a problem in that undesired data is outputted from the DRAM when an address is transited before a column address strobe signal is in active state. Further, since the undesired data is outputted, there occurs a problem of waste of electric power.